Q.1
Integer datatype is allocated ______ number of bits
  • 16
  • 32
  • 64
  • 8
Q.2
= and <= represent
  • Non-blocking and Blocking Assingment respectively
  • Blocking and Non-blocking Assingment respectively
Q.3
Reg [4:pwm will initialize variable of _______ bits
  • 3
  • 4
  • 5
  • 6
Q.4
{,} is used to perform which operation
  • concat
  • Division
  • Exponent
  • Mod
Q.5
Always construct is Synthesizable
  • True
  • False
Q.6
Initial statement is
  • Synthesizable
  • Not Synthesizable
Q.7
Which of the following are true with respect to arrays?
  • Dynamic arrays are useful for contiguous collection of variables whose number keeps varying
  • Associative arrays can be used when size of an array is not known as it can be built as key/value pairs
  • Dynamic arrays can be re-sized after size is allocated once
  • All of above
Q.8
Verilog may be written at the
  • Behavioral level
  • Structural level
  • dataflow level
  • All the above
Q.9
What is wrong with following piece of code int a, b; initial begin forever begin a=a+ b=b+ end end
  • Nothing wrong
  • incorrect a and b can overflow as it is incremented in an infinite loop
  • Simulation may not advance since forever doesn't have any timing control
  • A forever block cannot be used inside an initial block
Q.10
Both tasks and functions can be coded in a way to take ________inputs and return _____ outputs in System Verilog
  • Multiple, Single
  • Single, Multiple
  • Multiple, Multiple
  • Single, Single
Q.11
Which directive is used to include entire content of Verilog source Into another file?
  • 'include
  • 'ifdef
  • 'indef
  • None
Q.12
Which of the following is used for Verilog-based synthesis tools?
  • Intra-statement delay statements can be synthesized, but inter- statement delays cannot
  • Inter-statement delay statements can be synthesized, but intra- statement delays cannot
  • Initial values on wires are almost always ignored
  • Synthesized results are identical for “if” and “case” statements
Q.13
In most synthesis tools, what will happen when a signal that is needed in a sensitivity list is not included?
  • An error will be generated and the code cannot be synthesized
  • A warning message will be generated and the code will be synthesized but the resulting netlist will not provide the desired results
  • The synthesis tool will ignore the sensitivity list since all objects that are read as part of a procedural assignment statement are considered to be sensitive
  • There will be no effect on the design and pre-synthesis simulation will be consistent with post-synthesis simulation
Q.14
Variable and signal which will be updated first?
  • variable
  • signal
  • can't say
  • None of the above
Q.15
Which logic level is not supported by verilog?
  • U
  • X
  • Z
  • None of the above
Q.16
Which level of abstraction level is available in Verilog but not in VHDL?
  • Behavioral level
  • Structural level
  • Dataflow level
  • Switch level
Q.17
One particular pitfall is the accidental production of ________ rather than D-type flip-flops as storage elements.
  • Integrated circuit
  • Latch (electronics)
  • NAND gate
  • Logic gate
Q.18
The "structural"style of programming in Verilog _________the designer to use sequential semantics to define the behavior of a hardware component or block
  • does not allow
  • allows
  • allows with condition
  • None of the above
Q.19
VHDL uses an ___________declaration to describe how a component or block should perform
  • Architectural
  • Behavioral
  • Module
  • None of the above
Q.20
The input and output ports should be declared inside the ________
  • Module
  • Case
  • wire
  • None of the above
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