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Verilog
Quiz 3
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Q.1
The designers of Verilog wanted a language with syntax similar to the ________, which was already widely used in engineering software development
Pointer
python
C Programming
None of the above
Q.2
The symbol used for Logical AND operation is ______
and
or
&&
None
Q.3
The symbol used for bitwise AND operation is _____
and
or
$
&
Q.4
In behavioral modeling the keyword used is _______
always
become
and
or
Q.5
Different types of modelling in Verilog HDL are _____
Gate level, Data flow and Behavioral
data, case and type
Gate, Logic and gates
None
Q.6
The Verilog HDL code ends with the keyword_________
always
module
keys
endmodule
Q.7
The full form of VHDL is _____________
Very High Descriptive Language
Verilog Hardware Description Language
Variable Definition Language
None of the Mentioned
Q.8
The full form of HDL is _________________
Higher Descriptive Language
Higher Definition Language
Hardware Description Language
High Descriptive Language
Q.9
Verilog is an
Case Insensitive
Case Sensitive
Can't say
Q.10
Which of the following vector part selection is considered ILLEGAL for the given example:wire [7:bus;reg [0:virtual_add;
bus[5]
bus[1:0]
virtual_add[5:0]
virtual_add[0]
0 h : 0 m : 1 s
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