Q.1

Which of the following is an invalid output state for an 8421 BCD counter?

  • 1110
  • 0000
  • 0010
  • 0001
Q.2

How many different states does a 3-bit asynchronous counter have?

  • 2
  • 4
  • 8
  • 16
Q.3

A multiplexed display being driven by a logic circuit:

  • accepts data inputs from one line and passes this data to multiple output lines
  • accepts data inputs from several lines and allows one of them at a time to pass to the output
  • accepts data inputs from multiple lines and passes this data to multiple output lines
  • accepts data inputs from several lines and multiplexes this input data to four BCD lines
Q.4

List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.

  • RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
  • RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
  • RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
  • RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
Q.5

For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?

  • By using a counter
  • By using an active clock
  • By using an immediate reload
  • By using edge trapping
Q.6

The terminal count of a 3-bit binary counter in the DOWN mode is ________.

  • 000
  • 111
  • 101
  • 010
Q.7

The terminal count of a typical modulus-10 binary counter is ________.

  • 0000
  • 1010
  • 1001
  • 1111
Q.8

A 4-bit counter has a maximum modulus of ________.

  • 3
  • 6
  • 8
  • 16
Q.9

What is the difference between a 7490 and a 7492?

  • 7490 is a MOD-12, 7492 is a MOD-10
  • 7490 is a MOD-12, 7492 is a MOD-16
  • 7490 is a MOD-16, 7492 is a MOD-10
  • 7490 is a MOD-10, 7492 is a MOD-12
Q.10

List which pins need to be connected together on a 7492 to make a MOD-12 counter.

  • 1 to 12, 11 to 6, 9 to 7
  • 1 to 12, 12 to 6, 11 to 7
  • 1 to 12, 9 to 6, 8 to 7
  • 1 to 12
Q.11

Three cascaded modulus-5 counters have an overall modulus of ________.

  • 5
  • 25
  • 125
  • 500
Q.12

Which segments (by letter) of a seven-segment display need to be active in order to display a digit 6?

  • b, c, d, e, f, and g
  • a, c, d, e, f, and g
  • a, b, c, d, and f
  • b, c, d, e, and f
Q.13

Which of the following is an invalid state in an 8421 BCD counter?

  • 0011
  • 1001
  • 1000
  • 1100
Q.14

Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?

  • 50,000
  • 65,536
  • 25,536
  • 15,536
Q.15

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.

  • 12 ms
  • 24 ns
  • 48 ns
  • 60 ns
Q.16

What is meant by parallel load of a counter?

  • Each FF is loaded with data on a separate clock.
  • The counter is cleared.
  • All FFs are preset with data.
Q.17

Which is not an example of a truncated modulus?

  • 8
  • 9
  • 11
  • 15
Q.18

Four cascaded modulus-10 counters have an overall modulus of ________.

  • 10
  • 100
  • 1,000
  • 10,000
Q.19

The hexadecimal equivalent of 15,536 is ________.

  • 3CB0
  • 3C66
  • 63C0
  • 6300
Q.20

A seven-segment, common-anode LED display is designed for:

  • all cathodes to be wired together
  • one common LED
  • a HIGH to turn off each segment
  • disorientation of segment modules
Q.21

An asynchronous 4-bit binary down counter changes from count 2 to countHow many transitional states are required?

  • None
  • One
  • Two
  • Fifteen
Q.22

A BCD counter is a ________.

  • binary counter
  • full-modulus counter
  • decade counter
  • divide-by-10 counter
Q.23

Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?

  • Five flip-flops, three AND gates
  • Seven flip-flops, five AND gates
  • Four flip-flops, ten AND gates
  • Six flip-flops, four AND gates
Q.24

After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage sequence, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?

  • 0,1,0,1,1
  • 1,1,0,1,0
  • 1,0,1,0,1
  • 0,0,0,0,0
Q.25

A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?

  • 10002
  • 10102
  • 10112
  • 11012
Q.26

Which of the following is an example of a counter with a truncated modulus?

  • 8
  • 13
  • 16
  • 32
Q.27

Which of the following is a type of shift register counter?

  • Decade
  • Binary
  • Ring
  • BCD
Q.28

What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?

  • 15 ns
  • 22 ns
  • 60 ns
  • 88 ns
Q.29

In an HDL ring counter, many invalid states are included in the programming by:

  • using a case statement.
  • using an elsif statement.
  • including them under others.
  • the ser_in line.
Q.30

To operate correctly, starting a ring counter requires:

  • clearing one flip-flop and presetting all the others.
  • clearing all the flip-flops.
  • presetting one flip-flop and clearing all the others.
  • presetting all the flip-flops.
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