Q.1

The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:

  • external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs
  • modifying BCD counters to change states on every second input clock pulse
  • modifying asynchronous counters to change states on every second input clock pulse
  • elimination of the counter stages and the addition of combinational logic circuits to produce the desired counts
Q.2

The final output of a modulus-8 counter occurs one time for every ________.

  • 8 clock pulses
  • 16 clock pulses
  • 24 clock pulses
  • 32 clock pulses
Q.3

A 22-MHz clock signal is put into a MOD-16 counter. What is the frequency of the Q output of each stage of the counter?

  • Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz
  • Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
  • Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHz
  • Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz
Q.4

How many different states does a 2-bit asynchronous counter have?

  • 1
  • 2
  • 4
  • 8
Q.5

The terminal count of a modulus-11 binary counter is ________.

  • 1010
  • 1000
  • 1001
  • 1100
Q.6

A 4-bit counter has a maximum modulus of ________.

  • 3
  • 6
  • 8
  • 16
Q.7

Three cascaded decade counters will divide the input frequency by ________.

  • 10
  • 20
  • 100
  • 1,000
Q.8

In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

  • A trigger edge has occurred and we must load the counter.
  • The counter is zero and we need to keep it at zero.
  • The shift register is reset.
  • The counter is not zero and we need to count down by one.
Q.9

Three cascaded decade counters will divide the input frequency by ________.

  • 10
  • 20
  • 100
  • 1,000
Q.10

A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.

  • 10 kHz
  • 20 kHz
  • 30 kHz
  • 60 kHz
Q.11

List which pins need to be connected together on a 7493 to make a MOD-12 counter.

  • 12 to 1, 11 to 3, 9 to 2
  • 12 to 1, 11 to 3, 12 to 2
  • 12 to 1, 11 to 3, 8 to 2
  • 12 to 1, 11 to 3, 1 to 2
Q.12

Which of the following is a type of shift register counter?

  • Decade
  • Binary
  • Ring
  • BCD
Q.13

Three cascaded decade counters will divide the input frequency by ________.

  • 10
  • 20
  • 100
  • 1,000
Q.14

How can a digital one-shot be implemented using HDL?

  • By using a resistor and a capacitor
  • By applying the concept of a counter
  • By using a library function
  • By applying a level trigger
Q.15

List which pins need to be connected together on a 7492 to make a MOD-12 counter.

  • 1 to 12, 11 to 6, 9 to 7
  • 1 to 12, 12 to 6, 11 to 7
  • 1 to 12, 9 to 6, 8 to 7
  • 1 to 12
Q.16

A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?

  • Yes
  • No
Q.17

A 4-bit counter has a maximum modulus of ________.

  • 3
  • 6
  • 8
  • 16
Q.18

Three cascaded decade counters will divide the input frequency by ________.

  • 10
  • 20
  • 100
  • 1,000
Q.19

A BCD counter is a ________.

  • binary counter
  • full-modulus counter
  • decade counter
  • divide-by-10 counter
Q.20

What type of register is shown below?

  • Parallel in/parallel out register
  • Serial in/parallel out register
  • Serial/parallel-in parallel-out register
  • Parallel-access shift register
Q.21

A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?

  • Yes
  • No
Q.22

The designation means that the ________.

  • up count is active-HIGH, the down count is active-LOW
  • up count is active-LOW, the down count is active-HIGH
  • up and down counts are both active-LOW
  • up and down counts are both active-HIGH
Q.23

The designation means that the ________.

  • up count is active-HIGH, the down count is active-LOW
  • up count is active-LOW, the down count is active-HIGH
  • up and down counts are both active-LOW
  • up and down counts are both active-HIGH
Q.24

Bidirectional shift registers can shift data either right or left.

  • True
  • False
Q.25

Modulus refers to ________.

  • a method used to fabricate decade counter units
  • the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
  • an input on a counter that is used to set the counter state, such as UP/DOWN
  • the maximum number of states in a counter sequence
Q.26

A BCD counter has ________ states.

  • 8
  • 9
  • 10
  • 11
Q.27

It is a characteristic of ring counters that the ________ equal to the number of flip-flops in the register.

  • number of invalid states is
  • number of CASE statements is
  • modulus is
  • other states are
Q.28

A(n) ________ one-shot starts a pulse in response to a trigger and will restart the internal pulse timer every time a subsequent trigger edge occurs before the pulse is complete.

  • non-retriggerable
  • retriggerable
  • high-level triggered
  • edge-triggered
Q.29

In many cases, counters must be strobed in order to eliminate glitches.

  • True
  • False
Q.30

Asynchronous counters are often called ________ counters.

  • toggle
  • ripple
  • binary
  • flip-flop
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