In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.

The stepper motor HDL will ignore its counter inputs and pass control inputs directly to the output when set in mode ________.

Each ________, starting at the simplest level, should be built in HDL.

In the digital clock design, the hours section is different from the seconds and minutes section in that it never goes to ________.

In the keypad encoder, the ________ must hold in its current state until a key is released.

In the digital clock project, the ENT input and RCO output can be used for synchronous counter cascading.

In the VHDL code of the stepper motor, the cout outputs are bit_vector type because they are binary bit patterns.

The direct drive mode of a stepper motor allows for less control by the operator.

In the keypad HDL encoder, the freeze bit detects when a key is released.

In the digital clock project, frequency prescaling is used to take a 1 pps input and transform it into a 60 pps timing signal.

In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.

In the keypad HDL encoder, the data signal is used to combine the row and column encoder data to make a 4-bit value representing the key that was pressed.

In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.

The full-step sequence of a stepper motor always has two coils energized in any state of the sequence and typically causes ________ of shaft rotation per step.

Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state.

In the keypad encoder, the ________ activate(s) the freeze bit only when one column is low.

In the digital clock project, a 60 pps input is transformed into a 1 pps timing signal. The block is called ________.

The interface of the stepper motor needs to operate in one of ________ mode(s).

In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.

In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce sine wave pulses at the rate of 60 pps.