Q.1

Why should a real hardware functional test be performed on the HDL stepper motor design?

  • To check the speed of the software
  • To check the current levels in the motor
  • To check the voltage levels of the real outputs
  • To provide a fully operational system
Q.2

In an HDL stepper motor design, why is there more than one mode?

  • To change the speed of the stepper motor
  • To change the direction of the stepper motor
  • To direct drive the stepper motor
  • All of the above
Q.3

In the frequency counter, what is the function of the Schmitt trigger circuit?

  • To reduce input noise
  • To condition the input signal
  • To convert non-square waveforms
  • To provide a usable signal to the display unit
Q.4

In the keypad application, what does the data signal define?

  • The row and column encoded data
  • The ring encoded data
  • The freeze locator data
  • The ring counter data
Q.5

What does the major block of an HDL code emulation of a keypad include?

  • A sequencer
  • A clock
  • A multiplexer
  • A ring counter
Q.6

Which is not a major block of an HDL frequency counter?

  • Display register
  • Decoder/display
  • Timing and control unit
  • Bit shifter
Q.7

In a full-step sequence involving two flip-flops driving four coils of a stepper motor, how far will the stepper motor step?

  • 90°
  • 45°
  • 30°
  • 15°
Q.8

List three basic blocks in the digital clock project.

  • MOD-60, MOD-12 counters
  • MOD-5, MOD-10, MOD-12 counters
  • MOD-60, MOD-10 counters
  • MOD-6, MOD-12, and MOD-10 counters
Q.9

When designing an HDL digital system, which is the worst mistake one can make?

  • Concluding that a fundamental block works perfectly
  • Failing to provide proper documentation
  • Adding blocks of code prior to testing them
  • Overlooking a possible VARIABLE
Q.10

What does the ring counter in the HDL keypad application do when a key is pressed?

  • Count to find the row
  • Freeze
  • Count to find the column
  • Start the D flip-flop
Q.11

Which is not a step in strategic planning for HDL development?

  • There must be a way to test each piece.
  • Each block must fit together to make up the whole system.
  • The names of each input and output must be known.
  • The exact operation of each block must be thoroughly defined and understood.
Q.12

The accuracy of the frequency counter depends on the:

  • system clock frequency.
  • number of displayed digits.
  • sampling rate.
  • display update rate.
Q.13

Which is not a step used to define the scope of an HDL project?

  • Are the inputs and outputs active HIGH or active LOW?
  • A clear vision of how to make each block work
  • What are the speed requirements?
  • How many bits of data are needed?
Q.14

In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?

  • It goes HIGH.
  • It goes LOW.
  • It goes to Hi-Z.
  • It goes to 1111H.
Q.15

In the digital clock project, the purpose of the frequency prescaler is to:

  • find the basic frequency.
  • transform a 60 pps input to a 1 pps timing signal.
  • prevent the clock from exceeding 12:59:59.
  • allow the BCD display to have a value from 00–59.
Q.16

Which is not a step that should be followed in project management?

  • Overall definition
  • System documentation
  • Synthesis and testing
  • System integration
Q.17

In the frequency counter, when is the new count stored in the display register?

  • After disabling the counter
  • When the count buffer is full
  • After the sample interval is set
  • When the timing and control block has put it there
Q.18

In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?

  • 6
  • 5
  • 4
  • 3
Q.19

In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?

  • 1 pulse per minute
  • 6 pulses per minute
  • 10 pulses per minute
  • 1 pulse per hour
Q.20

For the frequency counter, which is not a control signal from the control and timing block?

  • Clear
  • Enable
  • Reset
  • Store
0 h : 0 m : 1 s