Q.1

In the keypad application, what does the preset state of the ring counter define?

  • The proper output of the column encoder
  • The NANDing of the rows
  • The NANDing of the columns
  • The proper output of the row encoder
Q.2

What are two ways to remember the current state of a counter in VHDL?

  • With FUNCTIONS and PROCESS
  • With counters and timers
  • With SIGNAL and VARIABLE
  • With bit types
Q.3

In the digital clock project, what type of counter is used to count to 59 seconds?

  • MOD-60
  • MOD-6
  • BCD
  • BCD followed by a MOD-6
Q.4

What must a stepper motor HDL application include?

  • Variables and processes
  • Types and bits
  • Counters and decoders
  • Sequencers and multiplexers
Q.5

In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?

  • On
  • Off
  • Hi-Z
  • 1011
Q.6

In a frequency counter, what happens at high frequencies when the sampling interval is too long?

  • The counter works fine.
  • The counter undercounts the frequency.
  • The measurement is less precise.
  • The counter overflows.
Q.7

In the digital clock project, when does the PM indicator go high?

  • Never
  • Going from 11:59:59 to 12:00:00
  • Going from 12:59:59 to 01:00:00
  • On the falling edge of the clock after enable goes high
Q.8

How is the output frequency related to the sampling interval of a frequency counter?

  • Directly with the sampling interval
  • Inversely with the sampling interval
  • More precision with longer sampling interval
  • Less precision with longer sampling interval
Q.9

In an HDL application of a stepper motor, after an up/down counter is built what is done next?

  • Build the sequencer
  • Test it on a simulator
  • Test the decoder
  • Design an intermediate integer variable
Q.10

In a digital clock application, the basic frequency must be divided down to:

  • 1 Hz.
  • 60 Hz.
  • 100 Hz.
  • 1000 Hz.
0 h : 0 m : 1 s