Q.1

One example of the use of an S-R flip-flop is as a(n):

  • racer
  • astable oscillator
  • binary storage register
  • transition pulse generator
Q.2

Which of the following describes the operation of a positive edge-triggered D flip-flop?

  • If both inputs are HIGH, the output will toggle.
  • The output will follow the input on the leading edge of the clock.
  • When both inputs are LOW, an invalid state exists.
  • The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Q.3

In VHDL, in which declaration section is a COMPONENT declared?

  • Architecture
  • Library
  • Entity
  • Port map
Q.4

Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.

  • True
  • False
Q.5

What is the hold condition of a flip-flop?

  • both S and R inputs activated
  • no active S or R input
  • only S is active
  • only R is active
Q.6

To completely load and then unload an 8-bit register requires how many clock pulses?

  • 2
  • 4
  • 8
  • 16
Q.7

Edge-triggered flip-flops must have:

  • very fast response times.
  • at least two inputs to handle rising and falling edges.
  • a pulse transition detector.
  • active-LOW inputs and complemented outputs.
Q.8

What is the difference between the 7476 and the 74LS76?

  • the 7476 is master-slave, the 74LS76 is master-slave
  • the 7476 is edge-triggered, the 74LS76 is edge-triggered
  • the 7476 is edge-triggered, the 74LS76 is master-slave
  • the 7476 is master-slave, the 74LS76 is edge-triggered
Q.9

Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.

  • True
  • False
Q.10

What does the triangle on the clock input of a J-K flip-flop mean?

  • level enabled
  • edge-triggered
Q.11

Which of the following is not generally associated with flip-flops?

  • Hold time
  • Propagation delay time
  • Interval time
  • Set up time
Q.12

An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.

  • HIGHs are applied simultaneously to both inputs S and R
  • LOWs are applied simultaneously to both inputs S and R
  • a LOW is applied to the S input while a HIGH is applied to the R input
  • a HIGH is applied to the S input while a LOW is applied to the R input
Q.13

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.

  • SET
  • RESET
  • clear
  • invalid
Q.14

In VHDL, how many inputs will a primitive JK flip-flop have?

  • 2
  • 3
  • 4
  • 5
Q.15

What is one disadvantage of an S-R flip-flop?

  • It has no enable input.
  • It has an invalid state.
  • It has no clock input.
  • It has only a single output.
Q.16

As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:

  • very long.
  • very short.
  • at a maximum value to enable the input control signals to stabilize.
  • of no consequence as long as the levels are within the determinate range of value.
Q.17

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.

  • True
  • False
Q.18

The pulse width of a one-shot circuit is determined by ________.

  • a resistor and capacitor
  • two resistors
  • two capacitors
  • none of the above
Q.19

Which is not an Altera primitive port identifier?

  • clk
  • ena
  • clr
  • prn
Q.20

Which of the following is correct for a gated D flip-flop?

  • The output toggles if one of the inputs is held HIGH.
  • Only one of the inputs can be HIGH at a time.
  • The output complement follows the input when enabled.
  • Q output follows the input D when the enable is HIGH.
Q.21

Most people would prefer to use ________ over HDL.

  • graphic descriptions
  • functions
  • VHDL
  • AHDL
Q.22

Which of the following is correct for a D latch?

  • The output toggles if one of the inputs is held HIGH.
  • Q output follows the input D when the enable is HIGH.
  • Only one of the inputs can be HIGH at a time.
  • The output complement follows the input when enabled.
Q.23

When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.

  • be invalid
  • not change
  • remain unchanged
  • toggle
Q.24

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

  • constantly LOW
  • constantly HIGH
  • a 20 kHz square wave
  • a 10 kHz square wave
Q.25

If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

  • An invalid state will exist.
  • No change will occur in the output.
  • The output will toggle.
  • The output will reset.
Q.26

Edge-triggered flip-flops must have:

  • very fast response times
  • at least two inputs to handle rising and falling edges
  • positive edge-detection circuits
  • negative edge-detection circuits
Q.27

Which of the following is correct for a D latch?

  • The output toggles if one of the inputs is held HIGH.
  • Q output follows the input D when the enable is HIGH.
  • Only one of the inputs can be HIGH at a time.
  • The output complement follows the input when enabled.
Q.28

Which of the following best describes the action of pulse-triggered FF's?

  • The clock and the S-R inputs must be pulse shaped.
  • The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
  • A pulse on the clock transfers data from input to output.
  • The synchronous inputs must be pulsed.
Q.29

A positive edge-triggered D flip-flop will store a 1 when ________.

  • the D input is HIGH and the clock transitions from HIGH to LOW
  • the D input is HIGH and the clock transitions from LOW to HIGH
  • the D input is HIGH and the clock is LOW
  • the D input is HIGH and the clock is HIGH
Q.30

If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?

  • An invalid state will exist.
  • No change will occur in the output.
  • The output will toggle.
  • The output will reset.
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