Q.1

Edge-triggered flip-flops must have:

  • very fast response times
  • at least two inputs to handle rising and falling edges
  • positive edge-detection circuits
  • negative edge-detection circuits
Q.2

Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

  • active-HIGH
  • active-LOW
Q.3

Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

  • active-HIGH
  • active-LOW
Q.4

Which is not a real advantage of HDL?

  • Using higher levels of abstraction
  • Tailoring components to exactly fit the needs of the project
  • The use of graphical tools
  • Using higher levels of abstraction and tailoring components to exactly fit the needs of the project
Q.5

For an S-R flip-flop to be set or reset, the respective input must be:

  • installed with steering diodes
  • in parallel with a limiting resistor
  • LOW
  • HIGH
Q.6

The timing network that sets the output frequency of a 555 astable circuit contains ________.

  • three external resistors are used
  • two external resistors and an external capacitor are used
  • an external resistor and two external capacitors are used
  • no external resistor or capacitor is required
Q.7

With regard to a D latch, ________.

  • the Q output follows the D input when EN is LOW
  • the Q output is opposite the D input when EN is LOW
  • the Q output follows the D input when EN is HIGH
  • the Q output is HIGH regardless of EN's input state
Q.8

In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.

  • function
  • signal
  • semicolon
  • colon
Q.9

A J-K flip-flop is in a "no change" condition when ________.

  • J = 1, K = 1
  • J = 1, K = 0
  • J = 0, K = 1
  • J = 0, K = 0
Q.10

A gated S-R flip-flop goes into the CLEAR condition when ________.

  • S is HIGH; R is LOW; EN is HIGH
  • S is LOW; R is HIGH; EN is HIGH
  • S is LOW; R is HIGH; EN is LOW
  • S is HIGH; R is LOW; EN is LOW
Q.11

A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

  • CLK = NGT, D = 0
  • CLK = PGT, D = 0
  • CLOCK NGT, D = 1
  • CLOCK PGT, D = 1
  • CLK = NGT, D = 0, CLOCK NGT, D = 1
Q.12

If an input is activated by a signal transition, it is ________.

  • edge-triggered
  • toggle triggered
  • clock triggered
  • noise triggered
Q.13

The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

  • edge-detection circuit.
  • NOR latch.
  • NAND latch.
  • pulse-steering circuit.
Q.14

A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

  • CLK = NGT, D = 0
  • CLK = PGT, D = 0
  • CLOCK NGT, D = 1
  • CLOCK PGT, D = 1
  • CLK = NGT, D = 0, CLOCK NGT, D = 1
Q.15

Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.

  • 00
  • 11
  • 01
  • 10
Q.16

If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?

  • No change will occur in the output.
  • An invalid state will exist.
  • The output will toggle.
  • The output will reset.
Q.17

What is the difference between the enable input of the 7475 and the clock input of the 7474?

  • The 7475 is edge-triggered.
  • The 7474 is edge-triggered.
Q.18

How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

  • It can't be done.
  • Invert the Q outputs.
  • Invert the S-R inputs.
Q.19

The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.

  • one resistor
  • two resistors
  • one capacitor
  • a resistor and a capacitor
Q.20

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

  • clock is LOW
  • slave is transferring
  • flip-flop is reset
  • clock is HIGH
Q.21

If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.

  • S-C flip-flop
  • D flip-flop
  • gated S-C flip-flop
  • TOGGLE flip-flop
Q.22

The ________ is the time interval immediately following the active transition of the clock signal.

  • hold time
  • setup time
  • over-time
  • hang-time
Q.23

What type of multivibrator is a latch?

  • Astable
  • Monostable
  • Bistable
  • It depends on the type of latch.
Q.24

When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.

  • S = 1, R = 1
  • S = 1, R = 0
  • S = 0, R = 1
  • S = 0, R = 0
Q.25

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

  • the clock pulse is LOW
  • the clock pulse is HIGH
  • the clock pulse transitions from LOW to HIGH
  • the clock pulse transitions from HIGH to LOW
Q.26

A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

  • The power supply is probably noisy.
  • The switch contacts are bouncing.
  • The socket contacts on the register IC are corroded.
  • The register IC is intermittent and failure is imminent.
Q.27

What is one disadvantage of an S-R flip-flop?

  • It has no enable input.
  • It has an invalid state.
  • It has no clock input.
  • It has only a single output.
Q.28

On a J-K flip-flop, when is the flip-flop in a hold condition?

  • J = 0, K = 0
  • J = 1, K = 0
  • J = 0, K = 1
  • J = 1, K = 1
Q.29

A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?

  • The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
  • The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
  • A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
  • A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.
Q.30

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

  • 16
  • 8
  • 4
  • 2
0 h : 0 m : 1 s