Q.1

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

  • cross coupling
  • gate impedance
  • low input voltages
  • asynchronous operation
Q.2

What is one disadvantage of an S-R flip-flop?

  • It has no enable input.
  • It has an invalid state.
  • It has no clock input.
  • It has only a single output.
Q.3

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.

  • 1 kHz
  • 2 kHz
  • 4 kHz
  • 16 kHz
Q.4

The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.

  • parity error checking
  • ones catching
  • digital discrimination
  • digital filtering
Q.5

When is a flip-flop said to be transparent?

  • when the Q output is opposite the input
  • when the Q output follows the input
  • when you can see through the IC packaging
Q.6

The major advantage of a Schmitt trigger input is that it ________.

  • avoids erratic triggering
  • has more triggering methods
  • has a wider range of outputs
  • can be retriggered
Q.7

The action of ________ a FF or latch is also called resetting.

  • breaking
  • clearing
  • freeing
  • changing
Q.8

A gated S-R flip-flop is in the hold condition whenever ________.

  • the Gate Enable is HIGH
  • the Gate Enable is LOW
  • the S and R inputs are both LOW
  • the Gate Enable is HIGH and the S and R inputs are both LOW
Q.9

If an input is activated by a signal transition, it is ________.

  • hair-triggered
  • line-triggered
  • pulse-triggered
  • edge-triggered
Q.10

Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.

  • PROCESS
  • computer
  • simulator
  • primitive library
Q.11

The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.

  • capacitor
  • inductor
  • resistor
  • LED
Q.12

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

  • the clock pulse is LOW
  • the clock pulse is HIGH
  • the clock pulse transitions from LOW to HIGH
  • the clock pulse transitions from HIGH to LOW
Q.13

What is the significance of the J and K terminals on the J-K flip-flop?

  • There is no known significance in their designations.
  • The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
  • The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
  • All of the other letters of the alphabet are already in use.
Q.14

In VHDL, how is each instance of a component addressed?

  • A name followed by a colon and the name of the library primitive
  • A name followed by a semicolon and the component type
  • A name followed by the library being used
  • A name followed by the component library number
Q.15

What is another name for a one-shot?

  • Monostable
  • Multivibrator
  • Bistable
  • Astable
Q.16

The toggle mode is the mode in which a(n) ________ changes states for each clock pulse.

  • logic level
  • flip-flop
  • edge-detector circuit
  • toggle detector
Q.17

The signal used to identify edge-triggered flip-flops is ________.

  • a bubble on the clock input
  • an inverted "L" on the output
  • the letter "E" on the enable input
  • a triangle on the clock input
Q.18

Why are the S and R inputs of a gated flip-flop said to be synchronous?

  • They must occur with the gate.
  • They occur independent of the gate.
Q.19

The output of a gated S-R flip-flop changes only if the:

  • flip-flop is set
  • control input data has changed
  • flip-flop is reset
  • input data has no change
Q.20

On a master-slave flip-flop, when is the master enabled?

  • when the gate is LOW
  • when the gate is HIGH
  • both of the above
  • neither of the above
Q.21

The output pulse width for a 555 monostable circuit with R1 = 3.3 k and C1 = 0.02 F is ________.

  • 7.3 s
  • 73 s
  • 7.3 ms
  • 73 ms
Q.22

A 555 operating as a monostable multivibrator has a C1 = 100 F. Determine R1 for a pulse width of 500 ms.

  • 45
  • 455
  • 4.5 k
  • 455 k
Q.23

A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:

  • clock is LOW
  • slave is transferring
  • flip-flop is reset
  • clock is HIGH
Q.24

A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

  • The power supply is probably noisy.
  • The switch contacts are bouncing.
  • The socket contacts on the register IC are corroded.
  • The register IC is intermittent and failure is imminent.
Q.25

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.

  • 1 kHz
  • 2 kHz
  • 4 kHz
  • 16 kHz
Q.26

The advantage of a J-K flip-flop over an S-R FF is that ________.

  • it has fewer gates
  • it has only one output
  • it has no invalid states
  • it does not require a clock input
Q.27

An edge-triggered flip-flop can change states only when ________.

  • the trigger is HIGH
  • the D input is HIGH
  • the trigger is LOW
  • the trigger input changes levels
Q.28

The major advantage of a Schmitt trigger input is that it ________.

  • avoids erratic triggering
  • has more triggering methods
  • has a wider range of outputs
  • can be retriggered
Q.29

If an input is activated by a signal transition, it is ________.

  • hair-triggered
  • line-triggered
  • pulse-triggered
  • edge-triggered
Q.30

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

  • the clock pulse is LOW
  • the clock pulse is HIGH
  • the clock pulse transitions from LOW to HIGH
  • the clock pulse transitions from HIGH to LOW
0 h : 0 m : 1 s