Q.1

A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?

  • The power supply is probably noisy.
  • The switch contacts are bouncing.
  • The socket contacts on the register IC are corroded.
  • The register IC is intermittent and failure is imminent.
Q.2

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________.

  • 1 kHz
  • 2 kHz
  • 4 kHz
  • 16 kHz
Q.3

The symbols on this flip-flop device indicate ________.

  • triggering takes place on the negative-going edge of the CLK pulse
  • triggering takes place on the positive-going edge of the CLK pulse
  • triggering can take place anytime during the HIGH level of the CLK waveform
  • triggering can take place anytime during the LOW level of the CLK waveform
Q.4

The advantage of a J-K flip-flop over an S-R FF is that ________.

  • it has fewer gates
  • it has only one output
  • it has no invalid states
  • it does not require a clock input
Q.5

The advantage of a J-K flip-flop over an S-R FF is that ________.

  • it has fewer gates
  • it has only one output
  • it has no invalid states
  • it does not require a clock input
Q.6

The 7476 and 74LS76 are both dual flip-flops.

  • True
  • False
Q.7

All multivibrators require feedback.

  • True
  • False
Q.8

Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.

  • 10.24 kHz
  • 5 kHz
  • 30.24 kHz
  • 15 kHz
Q.9

A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.

  • True
  • False
Q.10

A D latch has one data-input line.

  • True
  • False
Q.11

VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code without relying on logic primitives.

  • True
  • False
Q.12

Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.

  • True
  • False
Q.13

In VHDL, each instance of a component is given a name followed by a semicolon and the name of the library primitive.

  • True
  • False
Q.14

Pulse-triggered or level-triggered devices are the same.

  • True
  • False
Q.15

The propagation delay time tPLH is measured from the triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

  • True
  • False
Q.16

Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

  • The logic level at the D input is transferred to Q on NGT of CLK.
  • The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
  • The Q output is ALWAYS identical to the D input when CLK = PGT.
  • The Q output is ALWAYS identical to the D input.
Q.17

Latches are tristate devices whose state normally depends on asynchronous inputs.

  • True
  • False
Q.18

Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.

  • True
  • False
Q.19

The 7474 has two distinct types of inputs: synchronous and asynchronous.

  • True
  • False
Q.20

The Q output of a flip-flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

  • True
  • False
Q.21

Some flip-flops have invalid states.

  • True
  • False
Q.22

The 555 timer can be used in either the astable or monostable modes.

  • True
  • False
Q.23

Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.

  • True
  • False
Q.24

A gated S-R flip-flop goes into the SET condition when S is HIGH, R is LOW, and EN is HIGH.

  • True
  • False
Q.25

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.

  • FUNCTION
  • logic primitive
  • VARIABLE
  • PROCESS
Q.26

An astable multivibrator is a circuit that ________.

  • has two stable states
  • is free-running
  • produces a continuous output signal
  • is free-running and produces a continuous output signal
Q.27

A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.

  • True
  • False
Q.28

It takes four flip-flops to act as a divide-by-4 frequency divider.

  • True
  • False
Q.29

The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.

  • True
  • False
Q.30

A latch can act as a contact-bounce eliminator.

  • True
  • False
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