Q.1

Propagation delay time, tPLH, is measured from the ________.

  • triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
  • triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
  • preset input to the LOW-to-HIGH transition of the output
  • clear input to the HIGH-to-LOW transition of the output
Q.2

Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.

  • True
  • False
Q.3

Most basic latches and flip-flops are available in IC packages of eight latches or flip-flops with a common clock.

  • True
  • False
Q.4

Edge-triggered flip-flops can be identified by the triangle on the clock input.

  • True
  • False
Q.5

An astable multivibrator is sometimes referred to as a clock.

  • True
  • False
Q.6

Multivibrators must be level-triggered.

  • True
  • False
Q.7

Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.

  • True
  • False
Q.8

ICs can perform sequential operations, including counting and data shifting.

  • True
  • False
Q.9

An input which can only be accepted when an enable or trigger is present is called asynchronous.

  • True
  • False
Q.10

The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.

  • True
  • False
Q.11

A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

  • True
  • False
Q.12

The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.

  • PRE, CLR, LOW
  • ON, OFF, HIGH
  • START, STOP, LOW
  • SET, RESET, HIGH
Q.13

Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.

  • True
  • False
Q.14

VHDL does require a special designation for an output with a feedback.

  • True
  • False
Q.15

A negative edge-triggered flip-flop will accept inputs only when the clock is LOW.

  • True
  • False
Q.16

The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.

  • Only S
  • S and R
  • Only D
  • All of the above.
Q.17

The gated S-R flip-flop is asynchronous.

  • True
  • False
Q.18

Connecting components together using HDL is not difficult.

  • True
  • False
Q.19

How is a J-K flip-flop made to toggle?

  • J = 0, K = 0
  • J = 1, K = 0
  • J = 0, K = 1
  • J = 1, K = 1
Q.20

A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.

  • True
  • False
Q.21

Parallel data transfers between two different sets of registers require more than one shift pulse.

  • True
  • False
Q.22

The 7475 is an example of an IC D latch (also called a bistable latch) that contains four transparent D latches.

  • True
  • False
Q.23

A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.

  • True
  • False
Q.24

Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.

  • set
  • reset
  • latch
  • toggle
Q.25

A one-shot circuit is also known as a timer.

  • True
  • False
Q.26

PRESET and CLEAR inputs are normally synchronous.

  • True
  • False
Q.27

Setup time specifies ________.

  • the minimum time for the control levels to be maintained on the inputs prior to the triggering edge of the clock in order for data to be reliably clocked into the FF
  • the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF
  • how long the operator has in order to get the flip-flop running before the maximum power level is exceeded
  • how long it takes the output to change states after the clock has transitioned
Q.28

The asynchronous inputs on a J-K flip-flop ________.

  • are normally not at the active level at the same time
  • take precedence over the J and K inputs
  • do not require a clock pulse to affect the output
  • all of the above
Q.29

How many flip-flops are in the 7475 IC?

  • 1
  • 2
  • 4
  • 8
Q.30

When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.

  • True
  • False
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