Q.1

In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.

  • traffic
  • D
  • flip-flop
  • clock
Q.2

The S-R flip-flop has no invalid or unused state.

  • True
  • False
Q.3

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

  • 3
  • 7
  • 10
  • 13
Q.4

A positive edge-triggered flip-flop will accept inputs only when the clock ________.

  • is LOW
  • changes from HIGH to LOW
  • is HIGH
  • changes from LOW to HIGH
Q.5

How many flip-flops are required to produce a divide-by-128 device?

  • 7
  • 1
  • 4
  • 6
Q.6

The key to edge-triggered sequential circuits in VHDL is the ________.

  • ARCHITECTURE
  • PROCESS
  • FUNCTION
  • VARIABLE
Q.7

The S-R flip-flop has no invalid or unused state.

  • True
  • False
Q.8

The S-R flip-flop has no invalid or unused state.

  • True
  • False
Q.9

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

  • 3
  • 7
  • 10
  • 13
Q.10

A flip-flop is in the CLEAR condition when .

  • True
  • False
Q.11

A J-K flip-flop and associated waveforms are shown below. The circuit is operating properly.

  • True
  • False
Q.12

PRESET and CLEAR inputs are normally synchronous.

  • True
  • False
Q.13

A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.

  • 3
  • 7
  • 10
  • 13
Q.14

A positive edge-triggered flip-flop will accept inputs only when the clock ________.

  • is LOW
  • changes from HIGH to LOW
  • is HIGH
  • changes from LOW to HIGH
Q.15

Assume an latch, made from cross-coupled NAND gates, has a 0 on both inputs. The outputs will be ________.

0 h : 0 m : 1 s