Q.1

The HIGH logic level for a standard TTL output must be at least ________.

  • 2.4 V
  • 2 V
  • 0.8 V
  • 5 V
Q.2

When the output of a standard TTL gate is HIGH, it can ________.

  • sink 16 mA of current from the attached input gates
    mu.gif
    mu.gif
  • source 400 A of current to no more than 10 attached gates
  • source 16 mA of current to no more than 10 attached gates
    mu.gif
  • sink a maximum of 400 A from no more than 10 load gates
Q.3

P-MOS and N-MOS ________.

  • represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
  • are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC
  • represent positive and negative MOS-type devices that can be operated from differential power supplies and are compatible with operational amplifiers
  • None of the above are.
Q.4

The time it takes for an input signal to pass through internal circuitry and generate the appropriate output effect is known as ________.

  • fan-out
  • propagation delay
  • rise time
  • fall time
Q.5

The output stage of a TTL gate is a special design called ________.

  • multiemitter
  • totem-pole
  • MSI
  • DIP
Q.6

What is unique about TTL devices such as the 74S00?

  • The gate transistors are silicon (S), and the gates therefore have lower values of leakage current.
  • The S denotes the fact that a single gate is present in the IC rather than the usual package of 2–6 gates.
  • The S denotes a slow version of the device, which is a consequence of its higher power rating.
  • The devices use Schottky transistors and diodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates into higher frequency operation.
Q.7

Which of the following summarizes the important features of ECL?

  • Low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption
  • Good noise immunity, negative logic, high frequency capability, low power dissipation, and short propagation time
  • Slow propagation time, high frequency response, low power consumption, and high output voltage swings
  • Poor noise immunity, positive supply voltage operation, good low frequency operation, and low power
Q.8

What must be done to interface CMOS to TTL?

  • A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL.
  • As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the CMOS is limited to two TTL gates.
  • A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates.
  • The two series cannot be interfaced without the use of special interface buffers designed for that purpose, such as the open-collector buffers.
Q.9

Which of the logic families listed below allows the highest operating frequency?

  • 74AS
  • ECL
  • HCMOS
  • 54S
Q.10

What must be done to interface TTL to CMOS?

  • A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL.
  • As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the TTL is limited to five CMOS gates.
  • A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates.
  • A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates connected to the node.
Q.11

Whenever a totem-pole TTL output goes from LOW to HIGH, a high-amplitude current spike is drawn from the Vcc supply. How is this effect corrected to a digital circuit?

  • By connecting a radio-frequency capacitor from Vcc to ground.
  • By using a switching power supply
  • By connecting a capacitor from Vout to ground
  • By connecting a large resistor from Vcc to Vout
Q.12

Which of the following logic families has the highest maximum clock frequency?

  • S-TTL
  • AS-TTL
  • HS-TTL
  • HCMOS
Q.13

Which of the logic families listed below allows the highest operating frequency?

  • 74AS
  • ECL
  • HCMOS
  • 54S
Q.14

The abbreviated designator for a HIGH input voltage is VIH.

  • True
  • False
Q.15

What is the static charge that can be stored by your body as you walk across a carpet?

  • 300 volts
  • 3,000 volts
  • 30,000 volts
  • Over 30,000 volts
Q.16

The major advantage of TTL logic circuits over CMOS is lower propagation delay.

  • True
  • False
Q.17

When the outputs of several open-collector TTL gates are connected together, the gate outputs ________.

  • usually burn out
  • produce more voltage
  • are ANDed together
  • produce more fan-out
Q.18

Generally, the voltage measured at an unused TTL input would typically be measured between:

  • 1.4 to 1.8 V.
  • 0 to 5 V.
  • 0 to 1.8 V.
  • 0.8 to 5 V.
Q.19

What causes low-power Schottky TTL to use less power than the 74XX series TTL?

  • The Schottky-clamped transistor
  • Nothing. The 74XX series uses less power.
  • A larger value resistor
  • Using NAND gates
Q.20

Why is the fan-out of CMOS gates frequency dependent?

  • Each CMOS input gate has a specific propagation time and this limits the number of different gates that can be connected to the output of a CMOS gate.
  • When the frequency reaches the critical value, the gate will only be capable of delivering 70% of the normal output voltage and consequently the output power will be one-half of normal; this defines the upper operating frequency.
  • The higher the number of gates attached to the output, the more frequently they will have to be serviced, thus reducing the frequency at which each will be serviced with an input signal.
  • The input gates of the FETs are predominantly capacitive, and as the signal frequency increases the capacitive loading also increases, thereby limiting the number of loads that may be attached to the output of the driving gate.
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