Q.1

One output structure of a TTL gate is often referred to as a ________.

  • totem-pole arrangement
  • diode arrangement
  • JBT arrangement
  • base, emitter, collector arrangement
Q.2

Which equation is correct?

  • VNL = VIL(max) + VOL(max)
  • VNH = VOH(min) + VIH(min)
  • VNL = VOH(min) – VIH(min)
  • VNH = VOH(min) – VIH(min)
Q.3

Which is not part of emitter-coupled logic (ECL)?

  • Differential amplifier
  • Bias circuit
  • Emitter-follower circuit
  • Totem-pole circuit
Q.4

A certain gate draws 1.8 A when its output is HIGH and 3.3 µA when its output is LOW. VCC is 5 V and the gate is operated on a 50% duty cycle. What is the average power dissipation (PD)?

  • 2.55 W
  • 1.27 W
  • 12.75 W
  • 5 W
Q.5

The greater the propagation delay, the ________.

  • lower the maximum frequency
  • higher the maximum frequency
  • maximum frequency is unaffected
  • minimum frequency is unaffected
Q.6

A pull-down resistor must be used with open-collector TTL circuits.

  • True
  • False
Q.7

The speed-power product provides a basis for the comparison of logic circuits when power dissipation and propagation delay are important considerations in the selection of the type of logic to be used.

  • True
  • False
Q.8

Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in CMOS circuits.

  • True
  • False
Q.9

There are four different logic level ranges for TTL and CMOS: VIL, VIH, VOL, and VOH.

  • True
  • False
Q.10

ECL IC technology is faster than TTL technology.

  • True
  • False
Q.11

Power dissipation is a measure of a circuit's noise immunity.

  • True
  • False
Q.12

The total sink current decreases with an increase in each load gate input.

  • True
  • False
Q.13

CMOS is a more dominant IC technology than TTL.

  • True
  • False
Q.14

Unused TTL inputs should be tied LOW.

  • True
  • False
Q.15

The greater the propagation delay, the higher the maximum frequency.

  • True
  • False
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