Q.1

The basic part numbers of ICs are the same regardless of the manufacturer because digital logic ICs have been standardized.

  • True
  • False
Q.2

In ECL, the HIGH and LOW levels are determined by which transistor in a differential amplifier is conducting more.

  • True
  • False
Q.3

How many 74LSTTL logic gates can be driven from a 74TTL gate?

  • 10
  • 20
  • 200
  • 400
Q.4

Which of the following logic families has the shortest propagation delay?

  • CMOS
  • BiCMOS
  • ECL
  • 74SXX
Q.5

Schottky logic overcomes the saturation and stored charge problem by placing a Schottky diode across the base-to-collector junction.

  • True
  • False
Q.6

Propagation delay in TTL is due to slow switching speeds.

  • True
  • False
Q.7

What is the difference between the 74HC00 series and the 74HCT00 series of CMOS logic?

  • The HCT series is faster.
  • The HCT series is slower.
  • The HCT series is input and output voltage compatible with TTL.
  • The HCT series is not input and output voltage compatible with TTL.
Q.8

Why must CMOS devices be handled with care?

  • so they don’t get dirty
  • because they break easily
  • because they can be damaged by static electricity discharge
Q.9

Interfacing (74HCMOS to 74ALSTTl or 74TTL to 74LSTTL) can be done with no danger.

  • True
  • False
Q.10

In TTL the noise margin is between 0.8 V and 0.4 V.

  • True
  • False
Q.11

Special handling precautions should be taken when working with MOS devices. Which of the following statements is not one of these precautions?

  • All test equipment should be grounded.
  • MOS devices should have their leads shorted together for shipment and storage.
  • Never remove or insert MOS devices with the power on.
  • Workers handling MOS devices should not have grounding straps attached to their wrists.
Q.12

A pulse is not perfectly square; it takes time for the digital level to rise from 0 up to 1 and to fall from 1 down to 0.

  • True
  • False
Q.13

The AND is the simplest of the gates, requiring the least amount of circuitry to implement in TTL.

  • True
  • False
Q.14

Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?

  • These are worst-case conditions.
  • These are normal conditions.
  • These are best-case conditions.
  • It doesn't matter what values are used.
Q.15

Why are the maximum value of VOL and the minimum value of VOH used to determine the noise margin rather than the typical values for these parameters?

  • These are worst-case conditions.
  • These are normal conditions.
  • These are best-case conditions.
  • It doesn't matter what values are used.
Q.16

PMOS and NMOS are commonly used for small memories and microprocessors.

  • True
  • False
Q.17

A typical fan-out for most TTL is 9.

  • True
  • False
Q.18

What should be done to unused inputs on TTL gates?

  • They should be left disconnected so as not to produce a load on any of the other circuits and to minimize power loading on the voltage source.
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  • All unused gates should be connected together and tied to V through a 1 k resistor.
  • All unused inputs should be connected to an unused output; this will ensure compatible loading on both the unused inputs and unused outputs.
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  • Unused AND and NAND inputs should be tied to VCC through a 1 k resistor; unused OR and NOR inputs should be grounded.
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