A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer interconnect that is used to connect internal logic modules is called a ________.

The FPLA has a programmable AND array and a programmable OR array.

LUT is an acronym for look-up table.

The MAX+PLUS II compiler will automatically program a macrocell to borrow up to six product terms from each of three adjacent macrocells in the same LAB.

Antifuse devices are volatile.

The PAL has an AND and OR structure similar to a PROM, but in the PAL the inputs to the AND gates are programmable, whereas the inputs to the OR gate are hard-wired.

The Altera FLEX10K family uses a look-up table (LUT) architecture.

PLDs cannot meet all the possible requirements of complex digital circuitry.

The schematic editor allows you to connect with predefined logic symbols.

VHDL code is divided into three sections: library declaration, entity declaration, and architecture body.

In a FLEX10K device, the carry chain provides a fast carry forward function between ________.

The Boolean expression (A + B)(C + D) is an example of ________.

The PAL structure is able to perform any sum-of-products (SOP) operation.

A PAL uses a programmable OR array followed by a fixed AND array.

The SRAM technology is volatile.

The major structures of the MAX7000S are the logic array block (LAB) and the programmable intermediate array (PIA).

With microcomputer/DSP systems, devices can be electronically controlled and data can be manipulated by executing a program of instructions that has been written for the application.

Gate arrays are ULSI circuits that offer hundreds of thousands of gates.

Schematic capture is a process performed by PLD software.

The four input-only pins found on devices in the MAX7000S family can be configured as specific high-speed control signals or as general user inputs.

All inputs to the MAX7000S device and all macrocell outputs feed the PIA.

An Altera FLEX10K device uses a(n) ________ architecture.

Using a hardware solution for your digital system design is always faster than a software solution.

All I/O pins in the MAX7000S family have a tristate buffer.

The major digital system categories include Boolean logic, ASICs, and microprocessor/DSP devices.

An expensive form of programmable logic is SPLD.

In the OLMC of a GAL16V8, the FMUX selects the signal that is fed into the input matrix.

A PAL consists of an array of fixed AND gates that are connected to a programmable array of OR gates.

Sum-of-products is two or more product terms that are NANDed together.

The ________ is the most popular standard logic device family today.