Q.1

A GAL is a programmable/reprogrammable PAL.

  • True
  • False
Q.2

Altera Corporation and Xilinx Corporation are the two leading PLD manufacturers.

  • True
  • False
Q.3

The GAL chip uses an EEPROM array that is erasable and reprogrammable at least 1000 times.

  • True
  • False
Q.4

Most PAL devices have a tristate buffer driving the input pins.

  • True
  • False
Q.5

Most complex digital designs include a mix of different hardware categories.

  • True
  • False
Q.6

What is the input/output pin configuration of the GAL22V10?

  • 10 output pins and 12 input pins
  • 2 special-purpose pins
  • 8 pins that are either inputs or outputs
  • All of the above
Q.7

Which is a mode of operation of the GAL16V8?

  • Simple mode
  • Complex mode
  • Registered mode
  • All of the above
Q.8

What is an EPM7128S?

  • An Altera MAX7000S CPLD
  • An Altera UP2
  • A DeVry eSOC
  • A BSR PL DT-2
Q.9

Which is not a part of a GAL16V8's OLMC?

  • TSMUX
  • OMUX
  • FMUX
  • PSMUX
Q.10

CLB is the acronym for ________.

  • Configurable Logic Block
  • Configurable Logic Buffer
  • Critical Logic Buffer
  • Constant Logic Buffer
Q.11

What does the Altera FLEX10K PLD use in place of AND and OR arrays?

  • Nothing, it uses AND and OR arrays.
  • Look-up tables
  • SRAM-based memory
  • HPLD architecture
Q.12

A(n) ________ consists of a programmable array of AND gates that connects to a fixed array of OR gates and is usually OTP.

  • GAL
  • CPLD
  • PAL
  • SPLD
Q.13

What is another name for digital circuitry called sequential logic?

  • logic macrocell
  • logic array
  • flip-flop memory circuitry
  • inverter
Q.14

FPLA is:

  • a nonmemory programmable device.
  • a programmable AND array.
  • a programmable OR array.
  • All of the above
Q.15

A look-up table is simply a truth table with all the possible output connections listed with their desired input response.

  • True
  • False
Q.16

Which of the following testing procedures uses the JTAG IEEE standard?

  • Bed-of-nails
  • Flying probe
  • EXTEST
  • Boundary scan
Q.17

The macrocells in a PAL/GAL are located ________.

  • after the programmable AND arrays
  • ahead of the programmable AND arrays
  • at the input terminals
  • at the output terminals
Q.18

An SPLD listed as 22V10 has ________.

  • 10 inputs, 10 outputs, and requires a 22 V power source
  • 11 inputs, 11 outputs, and requires a 10 V power source
  • 22 inputs and 10 outputs
  • 10 inputs and 22 outputs
Q.19

The Altera MAX 7000 series ________.

  • uses an E2PROM process technology
  • can have between 2 and 16 LABS and I/O control blocks
  • is available with DC supply voltages between 2.5 V and 5 V
  • all of the above
Q.20

What does a dot mean when placed on a PLD circuit diagram?

  • A point that is programmable
  • A point that cannot change
  • An intersection of logic blocks
  • An input or output point
Q.21

FPGA is the acronym for ________.

  • Flexible Programming [of] Generic Assemblies
  • Field Programmable Generic Array
  • Field Programmable Gate Array
  • Field Programmer's Gate Assembly
Q.22

What is PROM?

  • SPLD
  • QPLD
  • HPLD
  • PLD
Q.23

A slice consists of ________.

  • only two logic cells
  • between 2 and 8 logic cells
  • up to 16 logic cells
  • a single CLB
Q.24

What can the GAL22V10 do that the GAL16V8 cannot?

  • It has an extra-large array.
  • It is in-system programmable.
  • It has twice the special function pins.
  • All of the above
Q.25

PIA is an acronym for ________.

  • Programmable Interface Array
  • Post Integrated Array
  • Programmable Input Array
  • Programmable Interconnect Array
Q.26

When did the first PLD appear?

  • More than 10 years ago
  • More than 20 years ago
  • More than 30 years ago
  • More than 40 years ago
Q.27

A(n) ________ is a section of embedded logic that is commonly found in FPGAs.

  • LUT
  • core
  • DSP
  • PI
Q.28

The final step in the device programming sequence is ________.

  • compiling
  • downloading
  • simulation
  • synthesis
Q.29

How many macrocells are in a MAX700S LAB?

  • 8
  • 16
  • 32
  • 64
Q.30

Which of the following is true?

  • Altera uses PAL architecture and Xilinx uses PLA architecture.
  • Altera uses PLA architecture and Xilinx uses PAL architecture.
  • Altera and Xilinx both use PAL architecture.
  • Altera and Xilinx both use PLA architecture.
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