Q.1

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial stateAfter three clock pulses, the register contains ________.

  • 01110
  • 00001
  • 00101
  • 00110
Q.2

How many clock pulses will be required to completely load serially a 5-bit shift register?

  • 2
  • 3
  • 4
  • 5
Q.3

How is a strobe signal used when serially loading a shift register?

  • to turn the register on and off
  • to control the number of clocks
  • to determine which output Qs are used
  • to determine the FFs that will be used
Q.4

When the output of a tristate shift register is disabled, the output level is placed in a:

  • float state
  • LOW state
  • high-impedance state
  • float or high-impedance state
Q.5

To serially shift a nibble (four bits) of data into a shift register, there must be ________.

  • one clock pulse
  • four clock pulses
  • eight clock pulses
  • one clock pulse for each 1 in the data
Q.6

Computers operate on data internally in a ________ format.

  • tristate
  • universal
  • parallel
  • serial
Q.7

What is the difference between a shift-right register and a shift-left register?

  • There is no difference.
  • the direction of the shift
Q.8

The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?

  • 10011100
  • 11000000
  • 00001100
  • 11110000
Q.9

What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?

  • parallel-in, parallel-out
  • parallel-in, serial-out
  • serial-in, parallel-out
  • serial-in, serial-out
Q.10

In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns?

  • 2
  • 6
  • 12
  • 24
Q.11

If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?

  • 11101011
  • 00010111
  • 11110000
  • 00000000
Q.12

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibbleWhat will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

  • 1100
  • 0011
  • 0000
  • 1111
Q.13

In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?

  • 1
  • 2
  • 4
  • 8
Q.14

What is a transceiver circuit?

  • a buffer that transfers data from input to output
  • a buffer that transfers data from output to input
  • a buffer that can operate in both directions
Q.15

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.

  • 0000
  • 1111
  • 0111
  • 1000
Q.16

A 74HC195 4-bit parallel access shift register can be used for ________.

  • serial in/serial out operation
  • serial in/parallel out operation
  • parallel in/serial out operation
  • all of the above
Q.17

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

  • 1.67 s
  • 26.67 s
  • 26.7 ms
  • 267 ms
Q.18

What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?

  • parallel-in, parallel-out
  • parallel-in, serial-out
  • serial-in, parallel-out
  • serial-in, serial-out
Q.19

Which type of device may be used to interface a parallel data format with external equipment's serial format?

  • key matrix
  • UART
  • memory chip
  • series in, parallel out
Q.20

What are the three output conditions of a three-state buffer?

  • HIGH, LOW, float
  • 1, 0, float
  • both of the above
  • neither of the above
0 h : 0 m : 1 s