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Q.1
The timing difference between a slow memory and fast processor can be resolved if
Processor is capable of waiting
External buffer is used
Either A or B
Neither A nor B
Q.2
Which of the following is not treated as hexadecimal constant by assembler in 8085?
45 H
6 AFH
234
64 H
Q.3
IC 7485 cannot be cascadeD.
True
False
Q.4
Which memory has read operation, byte erase, byte write and chip erase?
RAM
UVEPROM
EEPROM
Both B and C
Q.5
For a memory with a 16-bit address space, the addressability is
16 bits
8 bits
2^16 bits
Cannot be determined
Q.6
A real number consists of
Integer part
Integer part and fraction part
Integer part, fraction part along with positive or negative sign
None of the above
Q.7
Using DeMorgan’s Theorem we can convert any AND-OR structure into
NAND-NAND
OR-NAND
NAND-NOR
NOR-NAND
Q.8
In 8086 the number of bytes which can be addressed directly is about
1000
10000
100000
one million
Q.9
A 37 bit mantissa has an accuracy of
6 decimal places
8 decimal places
10 decimal places
11 decimal places
Q.10
DS directive in 8085
Forces the assembler to reserve one byte of memory
Forces the assembler to reserve a specified number of bytes in the memory
Forces the assembler to reserve a specified number of consecutive bytes in the memory
None of the above
Q.11
Which of the following is a valid integer constant?
127
127.0
127
125 + 3
Q.12
In 8085
P flag is set when the result has even parity
P flag is set when the result has odd parity
P flag is reset when the result has odd parity
P flag is reset when the result has even parity
Q.13
In 8085 which addressing mode is also called inherent addressing?
Direct
Register
Implicit
Immediate
Q.14
If the sign bit of mantissa is 0 and the exponent is increased from a positive to a more negative number the result is
A larger floating point number
A smaller floating point number
Either A or B depending on the actual number
A negative floating point number
Q.15
The operating modes of 8255 A are called
Mode 0 and mode 1
Mode 0, mode 1 and mode 2
Mode 0 and mode 2
Mode 0, mode 2 and mode 3
Q.16
In a computer the data transfer between hard disk and CPU is nearly the same as that between diskette and CPU.
True
False
Q.17
Which of the following pair of gates can form a latch?
A pair of cross coupled OR
A pair of cross copled AND
A pair of cross coupled NAND
A cross coupled NAND/OR
Q.18
Assertion (A): Each memory chip has its own address latch.
Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip.
Both A and R are correct and R is correct explanation of A
Both A and R are correct but R is not correct explanation of A
A is correct R is wrong
A is wrong R is correct
Q.19
Because we wish to allow each ASCII code to occupy one location in memory, most memories are __________ addressable.
BYTE
NIBBLE
WORD (16 bits)
DOUBLEWORD (32 bits)
Q.20
We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates. Which of the following sets are logically complete
Set of {AND,OR}
Set of {EXOR, NOT}
Set of {AND,OR,NOT}
None of the above
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