The difference between analog voltage represented by two adjacent digital codes, or the analog step size, is the:
In a flash analog-to-digital converter, the output of each comparator is connected to an input of a:
Which of the following is a type of error associated with digital-to-analog converters (DACs)?
The primary disadvantage of the flash analog-to digital converter (ADC) is that:
Which is not an analog-to-digital (ADC) conversion error?
A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the analog output for the input code 0101.
Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to:
What is the resolution of a digital-to-analog converter (DAC)?
What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted digital-to-analog DAC converter?
The practical use of binary-weighted digital-to-analog converters is limited to:
The resolution of a 0–5 V 6-bit digital-to-analog converter (DAC) is:
The characteristic that a change of one binary step on the input of a digital-to-analog converter (DAC) should cause exactly one step change on the output is called ________.
________ analog-to-digital converters (ADCs) use no clock signal, because there is no timing or sequencing required.
Inaccurate analog-to-digital conversion may be due to ____________.
________ analog-to-digital converters (ADCs) have a fixed value of conversion time that is not dependent on the value of the analog input.
A binary-weighted resistor used in a digital-to-analog converter (DAC) is only practical up to a resolution of ________.
The problems of the binary-weighted resistor digital-to-analog converter (DAC) can be overcome by using ___________.
The relative accuracy of a digital-to-analog converter (DAC) is determined by settling time.
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