Q.1

NMOS devices use MOSFETs to implement the full range of logic gates using the universal NAND gate.

  • True
  • False
Q.2

A digital logic device used as a buffer should have what input/output characteristics?

  • high input impedance and high output impedance
  • low input impedance and high output impedance
  • low input impedance and low output impedance
  • high input impedance and low output impedance
Q.3

CMOS circuits consume less power than TTL circuits.

  • True
  • False
Q.4

ECL gates are noted for their high frequency capability and small output voltage swing.

  • True
  • False
Q.5

Schottky TTL logic gates overcome the problem of saturation delay time.

  • True
  • False
Q.6

What is the standard TTL noise margin?

  • 5.0 V
  • 0.2 V
  • 0.8 V
  • 0.4 V
Q.7

Due to the extremely low power requirements of CMOS logic circuits, any number of CMOS and TTL gates can be interconnected.

  • True
  • False
Q.8

Delay times and current/voltage values remain constant regardless of temperature or other operating conditions for robust circuits like TTL.

  • True
  • False
Q.9

Low power consumption achieved by CMOS circuits is due to which construction characteristic?

  • complementary pairs
  • connecting pads
  • DIP packages
  • small-scale integration
Q.10

The problem of interfacing IC logic families that have different supply voltages (VCCs) can be solved by using a:

  • level-shifter
  • tri-state shifter
  • translator
  • level-shifter or translator
Q.11

Large-scale integration (LSI) ICs contain between ______ and _______ interconnected components.

  • 15,000, 150,000
  • 1,500, 15,000
  • 180, 1,000
  • 180, 1,500
Q.12

PMOS and NMOS ____________________________.

  • represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
  • are enhancement type CMOS devices used to produce a series of high-speed logic known as 74HC
  • represent positive and negative MOS type devices that can be operated from differential power supplies and are compatible with operational amplifiers
  • none of the above
Q.13

A three-state output TTL can have three possible outputs: LOW, HIGH, or FLOATING.

  • True
  • False
Q.14

The range of a valid LOW input is:

  • 0.0 V to 0.4 V
  • 0.4 V to 0.8 V
  • 0.4 V to 1.8 V
  • 0.4 V to 2.4 V
Q.15

5400 TTL series logic chips are made to military specifications.

  • True
  • False
Q.16

Totem pole output circuits can change states faster than open-collector output circuits.

  • True
  • False
Q.17

A TTL totem pole circuit is designed so that the output transistors are:

  • always on together
  • providing phase splitting
  • providing voltage regulation
  • never on together
Q.18

The time needed for an output to change as the result of an input change is known as:

  • noise immunity
  • fanout
  • propagation delay
  • rise time
Q.19

Ten TTL loads per TTL driver is known as:

  • noise immunity
  • power dissipation
  • fanout
  • propagation delay
Q.20

One example of the use of a Schmitt trigger is as a(n) _____

  • astable oscillator
  • transition pulse generator
  • pulse shaper
  • buffer
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