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Jee Main Advanced Physics Chapter Wise Mock Test
Quiz 1
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Q.1
With an increase in temperature, the electrical conductivity of intrinsic semiconductor
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remains unchanged
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increases
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decrease
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first (b) then (c)
Explanation
Solution:
In an intrinsic semiconductor, raising the temperature thermally excites more electrons across the band gap, creating more free electron-hole pairs -- more charge carriers directly means higher conductivity (the opposite of what happens in a metal, where conductivity falls as rising temperature disrupts carrier motion).
Q.2
A 220 V A.C. supply is connected between points A and B. What will be the potential difference V across the capacitor?
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220V
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110V
0%
0V
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$220 \sqrt 2$ V
Explanation
Solution:
This is a half-wave peak-detector circuit: the diode only conducts when the AC input exceeds the capacitor's current voltage, charging the capacitor up toward the input's PEAK value and then holding it there once the diode cuts off as the input falls back down.
220V is the RMS rating of the AC supply, so its actual peak is 220√2 V -- and that's what the capacitor settles at.
Q.3
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NOR
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OR
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AND
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XOR
Explanation
Solution:
Each of the two input NAND gates has both its pins tied to the same single input, which makes it act as a plain NOT gate: the top one outputs Ā, the bottom one outputs B̄.
These feed into a third NAND gate: Y = NOT(Ā·B̄) = NOT(Ā)+NOT(B̄) (De Morgan's law) = A+B -- an OR gate overall.
Q.4
The breakdown in a reverse-biased p–n junction diode is more likely to occur due to (i) large velocity of the minority charge carriers if the doping concentration is small. (ii) large velocity of the minority charge carriers if the doping concentration is large. (iii) strong electric field in a depletion region if the doping concentration is small. (iv) strong electric field in the depletion region if the doping concentration is large. Which of the below represent the correct options
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(i) and (ii)
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(i) and (iv)
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(iii) and (iv)
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(i) and (iii)
Explanation
Solution:
Avalanche breakdown happens when the doping is light (a wide depletion region), letting the few minority carriers accelerate over a long distance and pick up a large velocity, triggering a collision cascade -- matching (i).
Zener breakdown happens when the doping is heavy (a narrow depletion region), concentrating the same reverse voltage into a much stronger electric field across that short distance, strong enough to pull electrons directly out of their bonds -- matching (iv).
Q.5
In a p-n junction diode not connected to any circuit
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The potential is the same everywhere
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The p-type side is ay a higher potential than the n-type side
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There is an electric field at the junction directed from the n-type side to the p-type side
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There is an electric field at the junction directed from the p-type side to the n-type side
Explanation
Solution:
At equilibrium, diffusion across the junction leaves the n-side slightly positive (having lost some electrons near the junction) and the p-side slightly negative (having lost some holes) -- so the built-in electric field this creates points from the higher-potential n-side toward the lower-potential p-side, opposing any further diffusion.
Q.6
In a common base amplifier, the phase difference between the input signal voltage and the output voltage is
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$\frac {\pi}{4}$
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$\pi$
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0
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$\frac {\pi}{2}$
Explanation
Solution:
In a common base configuration, the output (collector) current tracks the input (emitter) current directly, without the phase reversal that a common emitter stage introduces -- input and output stay in phase, a phase difference of 0.
Q.7
In the circuit below, A and B represent the two input, and C represents the output. The circuit represents
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NOT gate
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NAND gate
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OR Gate
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XOR Gate
Explanation
Solution:
Either diode conducts whenever its own input is high, pulling the output node C high through it; C is only pulled low by the resistor when BOTH A and B are low. That's exactly the truth table of an OR gate: output high if A is high, or B is high, or both.
Q.8
We have a circuit of four NAND gates as shown below Match the column
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p -> i, q -> ii ,r->ii, s -> i
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p -> i, q -> ii ,r->ii, s -> i
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p -> i, q -> ii ,r->i, s -> i
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p -> ii, q -> ii ,r->ii, s -> i
Explanation
Solution:
This is the standard 4-NAND-gate construction of an XOR gate: the first NAND combines A and B, and its output feeds into two more NAND gates alongside A and alongside B, whose outputs finally combine in a fourth NAND -- the whole arrangement computes Y = A XOR B.
A=1,B=1 → XOR=0 (p→i). A=1,B=0 → XOR=1 (q→ii). A=0,B=1 → XOR=1 (r→ii). A=0,B=0 → XOR=0 (s→i).
Q.9
A semiconductor has an electron concentration of $8 \times 10^{13}$ per cm3 and a hole concentration of $5 \times 10^{12}$ per cm3 . The electron mobility is 25000 cm2 V-1 s-1 and the hole mobility is 100 cm2 V-1 s-Then,
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the semiconductor is n-type
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the conductivity is 320 m mho cm-1
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Both (a) and (b)
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None of the above
Explanation
Solution:
Since the electron concentration (8×10¹³/cm³) is far larger than the hole concentration (5×10¹²/cm³), electrons are the majority carrier -- this makes it an n-type semiconductor.
Conductivity σ=e(nμ
n
+pμ
p
) = (1.6×10⁻¹ⁿ)[(8×10¹³)(25000)+(5×10¹²)(100)]
= (1.6×10⁻¹ⁿ)[2×10¹⁸+5×10¹⁴] ≈ (1.6×10⁻¹ⁿ)(2×10¹⁸) = 0.32 (Ω·cm)⁻¹ = 320 milli-mho/cm (the hole term is negligible next to the electron term).
Q.10
In the given circuit, the voltage across the load is maintained at 12 V. The current in the Zener diode varies from 0.50 mA. What is the maximum wattage of the diode?
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12W
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6 W
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.6 W
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1,2 W
Explanation
Solution:
Maximum power dissipated in the Zener is simply its regulated voltage times its maximum current: P = VI = 12V × 50mA = 0.6 W.
Q.11
In the middle of the depletion layer of the reverse-biased p-n junction, the
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The electric field is zero
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Potential is maximum
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The electric field is maximum
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Potential is zero
Explanation
Solution:
The electric field builds up from zero at the edges of the depletion region to its peak somewhere in the middle, then falls off again -- so the field is actually strongest, not zero, in the middle of the depletion layer. It's the potential that's changing most steeply there (since field is -dV/dx), while the field itself is exactly zero only right at the two edges.
Q.12
If the ratio of the concentration of the electrons to that of holes in a semiconductor is 7/5 and the ratio of the currents is 7/4, then the ratio of the drift velocities will be
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5/8
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5/4
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4/5
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4/7
Explanation
Solution:
Current for each carrier type is I ∝ (concentration) × (drift velocity), so I
n
/I
p
= (n/p) × (v
n
/v
p
).
7/4 = (7/5) × (v
n
/v
p
) ⇒ v
n
/v
p
= (7/4) ÷ (7/5) = (7/4)(5/7) = 5/4.
Q.13
The Boolean expression $P + \bar{P} Q$ , where P and Q are the inputs of the logic circuit, represents
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AND gate
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NAND gate
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NOT gate
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OR gate
Explanation
Solution:
Using P+P̄=1: P + P̄Q = (P+P̄)(P+Q) = 1×(P+Q) = P+Q -- exactly the OR operation.
Q.14
You are required to choose the correct one out of the given four responses and mark it as (a) If both assertion and reason are true and reason is the correct explanation of the assertion. (b) If both assertion and reason are true but reason is not correct explanation of the assertion. (c) If assertion is true, but reason is false. (d) If both assertion and reason are false. (e) If reason is true but assertion is false. Assertion: A diode lasers are used as optical sources in optical communication. Reason: Diode lasers consume less energy
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a
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b
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c
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d
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e
Explanation
Solution:
Assertion: true -- diode lasers are indeed widely used as light sources for optical fibre communication.
Reason: also true on its own (diode lasers are known for being energy-efficient) -- but that's not really why they're chosen for communication specifically; the real reasons are their compact size, ability to be modulated (switched) rapidly to encode a digital signal, and coherence matched to fibre transmission, not primarily their power consumption.
Q.15
You are required to choose the correct one out of the given four responses and mark it as (a) If both assertion and reason are true and reason is the correct explanation of the assertion. (b) If both assertion and reason are true but reason is not correct explanation of the assertion. (c) If assertion is true, but reason is false. (d) If both assertion and reason are false. (e) If reason is true but assertion is false. Assertion: The number of electrons in a p-type silicon semiconductor is less than the number of electrons in a pure silicon semiconductor at room temperature. Reason: It is due to the law of mass action
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a
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b
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c
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d
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e
Explanation
Solution:
The law of mass action for semiconductors states n×p = n
i
² (a fixed constant at a given temperature). Doping silicon p-type raises the hole concentration p far above n
i
, and since the product must stay fixed, the electron concentration n = n
i
²/p is correspondingly pushed down well below n
i
-- fewer electrons than in pure (intrinsic) silicon, exactly as the law of mass action requires.
Q.16
You are required to choose the correct one out of the given four responses and mark it as (a) If both assertion and reason are true and reason is the correct explanation of the assertion. (b) If both assertion and reason are true but reason is not correct explanation of the assertion. (c) If assertion is true, but reason is false. (d) If both assertion and reason are false. (e) If reason is true but assertion is false Assertion: Conductivity of the semiconductor increases with doping Reason: Doping raises the temperature of the Semi-conductor
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a
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b
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c
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d
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e
Explanation
Solution:
Doping does increase conductivity -- true, since it directly adds many more charge carriers. But doping does this by introducing impurity atoms that donate or accept carriers, not by heating the material -- doping itself has nothing to do with temperature, so the given reason is false.
Q.17
You are required to choose the correct one out of the given four responses and mark it as (a) If both assertion and reason are true and reason is the correct explanation of the assertion. (b) If both assertion and reason are true but reason is not correct explanation of the assertion. (c) If assertion is true, but reason is false. (d) If both assertion and reason are false. (e) If reason is true but assertion is false. Assertion: In a transistor, the base is made thin. Reason: A thin base makes the transistor stable
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a
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b
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c
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d
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e
Explanation
Solution:
A thin base is a real, standard transistor design choice -- true. But it's done to minimise how many carriers recombine while crossing the base, which is what gives the transistor a high current gain -- not for "stability," which is a different design consideration entirely. So the reason given is false.
Q.18
Which one of the diode is reverse biased
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A
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B
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C
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D
Explanation
Solution:
For each diode, check what would happen if it conducted (zero drop): the resistor would then sit directly between the two fixed end voltages, and conventional current through it would have to flow from the higher potential end to the lower one. If that required direction of current happens to run from the diode's cathode toward its anode, an ideal diode can't actually carry it -- so the diode must really be OFF, i.e. reverse biased. Working through all four circuits this way, option (D) is the one where the implied current direction is blocked, confirming it's the reverse-biased diode.
Q.19
Which of the following current must be zero in an unbiased PN junction diode?
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Current due to majority charge carriers (both electrons and holes).
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Current due to minority charge carriers (both electrons and holes)
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Current due to majority and minority charge carriers.
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Current due to majority and minority charge carriers (only holes).
Explanation
Solution:
At equilibrium with no external bias, diffusion of majority carriers across the junction is exactly balanced by drift of minority carriers swept along by the junction's own built-in field -- the two together produce zero net current. In the simplified picture used here, it's the minority-carrier contribution (with so few minority carriers available on each side) that's treated as effectively zero.
Q.20
The current gain of a transistor in common base arrangement is .The load resistance of the output circuit is $400 k \ohm$ and input resistance is $200 \ohm$, then
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Voltage gain=1900, Power gain=1850
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Voltage gain=1805, Power gain=1900
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Voltage gain=1800, Power gain=1805
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Voltage gain=1900, Power gain=1805
Explanation
Solution:
Voltage gain = α × (R
load
/R
in
) = α × (400000/200) = α × 2000.
Matching the given voltage gain of 1900 fixes α=0.95 -- the standard common-base current gain used in this problem.
Power gain = α × Voltage gain = 0.95 × 1900 = 1805.
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