Q.1
The 32-bit control register, that is used to hold global machine status, independent of the executed task is
  • a) CR0
  • b) CR2
  • c) CR3
  • d) All of the mentioned
Q.2
The descriptor table that thesupports is
  • a) GDT (Global descriptor table)
  • b) IDT (Interrupt descriptor table)
  • c) LDT (Local descriptor table)
  • d) All of the mentioned
Q.3
The registers that are together, known as system address registers are
  • a) GDTR and IDTR
  • b) IDTR and LDTR
  • c) TR and GDTR
  • d) LDTR and TR
Q.4
Which of the following is a system segment register?
  • a) GDTR
  • b) LDTR
  • c) IDTR
  • d) None of the mentioned
Q.5
The test register(s) that is provided byfor page caching is
  • a) test control registers
  • b) page cache registers
  • c) test control and test status registers
  • d) test control and page cache registers
Q.6
Among eight debug registers, DR0-DRthe registers that are reserved by Intel are
  • a) DR0, DR1, DR2
  • b) DR4, DR5
  • c) DR1, DR4
  • d) DR5, DR6, DR7
Q.7
The registers that are used to store four program controllable break point addresses are
  • a) DR5-DR7
  • b) DR0-DR1
  • c) DR6-DR7
  • d) DR0-DR3
Q.8
The register DR6 hold
  • a) break point status
  • b) break point control information
  • c) break point status and break point control information
  • d) none of the mentioned
Q.9
The flag bits that indicate the privilege level of current IO operations are
  • a) Virtual mode flag bits
  • b) IOPL flag bits
  • c) Resume flag bits
  • d) None of the mentioned
Q.10
The registers that are not available for programmers are
  • a) data and address registers
  • b) instruction pointers
  • c) segment descriptor registers
  • d) flag registers
0 h : 0 m : 1 s