Q.1
Which of the following doesn’t corresponds to NAND gate?
  • a)
  • b)
  • c)
  • d)
Q.2
What is the minimum number of NAND gates required to implement an EXOR gate?
  • a) 2
  • b) 3
  • c) 4
  • d) 5
Q.3
Which of the following logic describes the EXOR gate?
  • a) y <= ((not a) OR (not b)) AND ((not a) OR (not b));
  • b) y <= ((not a) OR b) AND (a OR (not b))
  • c) y <= ((not a) AND (not b)) OR ((not a) AND (not b));
  • d) y <= ((not a) AND b) OR (a AND (not b));
Q.4
What logic circuit is described by the following code? ARCHITECTURE gate OF my_gate IS BEGIN WITH ab SELECT y<= 0 WHEN “OR “10”; 1 WHEN OTHERS; END gate;
  • a) NAND
  • b) NOR
  • c) EXOR
  • d) EXNOR
Q.5
Sometimes gates modeled with ________ modeling may behave differently.
  • a) Dataflow
  • b) Behavioral
  • c) Structural
  • d) Structural and Behavioral
Q.6
The odd behavior of gates in dataflow modeling may be the result of ________
  • a) Sequential statements
  • b) Wrong logic definitions
  • c) Concurrency
  • d) Inappropriate assignments
Q.7
Which of the following option represents a structural model for not gate?
  • a)
  • b)
  • c)
  • d)
Q.8
In CPLD, there are many input switches arranged in a switch bank, if an AND gate is behaving oddly but could be the reason?
  • a) Incorrect interconnections
  • b) Concurrent execution of statements
  • c) Mismatch of ports name and switches
  • d) Wrong libraries included
Q.9
For gates, which of the following modeling style will corresponds to shortest code?
  • a) Behavioral
  • b) Data flow
  • c) Structural
  • d) Both data flow and behavioral
Q.10
Generally, structural modeling is used with another modeling style.
  • a) True
  • b) False
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